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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
DESCRIPTION
The HCPL-0600/0601 optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40C to +85C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10 kV/s.
HCPL-0601
FEATURES
* * * * * * * * Compact SO8 package Very high speed-10 MBit/s Superior CMR-10 kV/s Fan-out of 8 over -40C to +85C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E90700)
PACKAGE DIMENSIONS
0.164 (4.16) 0.144 (3.66)
SEATING PLANE
Pin 1
APPLICATIONS
* Ground loop elimination * LSTTL to TTL, LSTTL or 5-volt CMOS * Line receiver, data transmission * Data multiplexing * Switching power supplies * Pulse transformer replacement * Computer-peripheral interface
N/C 1 8 VCC
0.202 (5.13) 0.182 (4.63)
0.019 (0.48) 0.010 (0.25) 0.006 (0.16)
+2 VF _ 3
7 VE
0.143 (3.63) 0.123 (3.13)
6 VO
0.021 (0.53) 0.011 (0.28)
0.008 (0.20) 0.003 (0.08) 0.050 (1.27) TYP
0.244 (6.19) 0.224 (5.69)
N/C 4
5 GND
Lead Coplanarity : 0.004 (0.10) MAX
Single-channel circuit drawing
NOTE All dimensions are in inches (millimeters)
TRUTH TABLE (Positive Logic)
Input H L H L H L Enable H H L L NC NC Output L H H H L H
A 0.1 F bypass capacitor must be connected between pins 8 and 5. (See note 1)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
ABSOLUTE MAXIMUM RATINGS (No derating required up to 85C)
Parameter Storage Temperature Operating Temperature Lead Solder Temperature EMITTER DC/Average Forward Input Current Enable Input Voltage Not to exceed VCC by more than 500 mV Reverse Input Voltage Power Dissipation DETECTOR Supply Voltage Output Current Output Voltage Collector Output Power Dissipation VCC (1 minute max) IO VO PO 7.0 50 7.0 85 V mA V mW IF VE VR PI 50 5.5 5.0 45 mA V V mW Symbol TSTG TOPR TSOL Value -40 to +125 -40 to +85 260 for 10 sec Units C C C
RECOMMENDED OPERATING CONDITIONS
Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Enable Voltage, Low Level Enable Voltage, High Level Operating Temperature Fan Out (TTL load) Symbol IFL IFH VCC VEL VEH TA N Min 0 *6.3 4.5 0 2.0 -40 Max 250 15 5.5 0.8 VCC +85 8 Units A mA V V V C
*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or less
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
ELECTRICAL CHARACTERISTICS (TA = -40C to +85C Unless otherwise specified.) INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter EMITTER Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Input Diode Temperature Coefficient DETECTOR High Level Supply Current Low Level Supply Current Low Level Enable Current High Level Enable Current High Level Enable Voltage Low Level Enable Voltage Test Conditions (IF = 10 mA) TA =25C (IR = 10 A) (VF = 0, f = 1 MHz) (IF = 10 mA) (VCC = 5.5 V, IF = 0 mA) (VE = 0.5 V) (VCC = 5.5 V, IF = 10 mA) (VE = 0.5 V) (VCC = 5.5 V, VE = 0.5 V) (VCC = 5.5 V, VE = 2.0 V) (VCC = 5.5 V, IF = 10 mA) (VCC = 5.5 V, IF = 10 mA) (Note 2) Symbol VF BVR CIN VF/TA ICCH ICCL IEL IEH VEH VEL 5.0 60 -1.4 Min Typ** Max 1.8 1.75 Unit V V pF mV/C
7 9 -0.8 -0.6 2.0
10 13 -1.6 -1.6 0.8
mA mA mA mA V V
SWITCHING CHARACTERISTICS (TA = -40C to +85C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.)
AC Characteristics Propagation Delay Time to Output High Level Test Conditions Device All All All All All All Symbol TPLH TPHL |TPHL-TPLH| tr tf tELH Min 20 25 Typ 45 45 3 50 12 20 Max 75 100 75 100 35 Unit ns ns ns ns ns ns (Note 3) (TA =25C) (RL = 350, CL = 15 pF) (Fig. 12) (Note 4) (TA =25C) Propagation Delay Time to Output Low Level (RL = 350, CL = 15 pF) (Fig. 12) Pulse Width Distortion (RL = 350, CL = 15 pF) (Fig. 12) Output Rise Time (RL = 350, CL = 15 pF) (10-90%) (Note 5) (Fig. 12) Output Fall Time (RL = 350, CL = 15 pF) (Note 6) (Fig. 12) (90-10%) Enable Propagation (IF = 7.5 mA, VEH = 3.5 V) Delay Time (RL = 350, CL = 15 pF) to Output High Level (Note 7) (Fig. 13) Enable Propagation (IF = 7.5 mA, VEH = 3.5 V) Delay Time (RL = 350, CL = 15 pF) to Output Low Level (Note 8) (Fig. 13) Common Mode (RL = 350) (TA =25C) |VCM| = 10 V (IF = 0 mA, VOH (Min.) = 2.0 V) Transient Immunity (Note 9)(Fig. 14) |VCM| = 50 V (at Output High Level) Common Mode (RL = 350) (TA =25C) |VCM| = 10 V Transient Immunity (IF = 7.5 mA, VOL (Max.) = 0.8 V) (at Output Low Level) (Note 10)(Fig. 14) |VCM| = 50 V
All HCPL-0600 HCPL-0601 HCPL-0600 HCPL-0601
tEHL
20 10,000
ns
|CMH|
5000 10,000 10,000
V/s
|CMH|
5000 10,000
V/s
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
TRANSFER CHARACTERISTICS (TA = -40C to +85C Unless otherwise specified.)
DC Characteristics High Level Output Current Low Level Output Voltage Input Threshold Current Test Conditions (VCC = 5.5 V, VO = 5.5 V) (IF = 250 A, VE = 2.0 V) (Note 2) (VCC = 5.5 V, IF = 5 mA) (VE = 2.0 V, IOL = 13 mA) (Note 2) (VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA) Symbol IOH VOL IFT .35 3 Min Typ** Max 100 0.6 5 Unit A V mA
ISOLATION CHARACTERISTICS (TA = -40C to +85C Unless otherwise specified.)
Characteristics Input-Output Insulation Leakage Current Test Conditions (Relative humidity = 45%) (TA = 25C, t = 5 s) (VI-O = 3000 VDC) (Note 11) (RH < 50%, TA = 25C) (Note 11) ( t = 1 min.) (VI-O = 500 V) (Note 11) (f = 1 MHz) (Note 11) Symbol Min Typ** Max Unit
II-O
1.0*
A
Withstand Insulation Test Voltage Resistance (Input to Output) Capacitance (Input to Output) ** All typical values are at VCC = 5 V, TA = 25C
VISO RI-O CI-O
2500 1012 0.6
VRMS pF
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1F capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 3. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse. 4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse. 5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse. 6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse. 7. tELH - Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse. 8. tEHL - Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse. 9. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/s). 10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/s). 11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
TYPICAL PERFORMANCE CURVES
Fig. 1 Forward Current vs. Input Forward Voltage
100
HCPL-0601
Fig. 2 Output Voltage vs. Forward Current
6 TA = 25C VCC = 5V
IF - FORWARD CURRENT (mA)
10 TA = 85C 1 TA = 70C TA = 25C 0.1 TA = 0C TA = -40C
5
Vo - OUTPUT VOLTAGE (V)
4 RL = 350 3 RL = 1k 2
0.01
1
0.001 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
0 0 1 2 3 4 5
VF - FORWARD VOLTAGE (V)
IF - FORWARD INPUT CURRENT (mA)
Fig. 3 Input Threshold Current vs. Temperature
5 VCC = 5V VO = 0.6V 4
Fig. 4 High Level Output Current vs. Temperature
16
IOH - HIGH LEVEL OUTPUT CURRENT (A)
ITH - INPUT THRESHOLD CURRENT (mA)
14 12 10 8 6 4 2 0 VO = VCC = 5.5V VE = 2V IF = 250 A -40 -20 0 20 40 60 80 100
3 RL = 350 2 RL = 1K
1
0 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
Fig. 5 Low Level Output Voltage vs. Temperature
0.8 V = 5.5V
HCPL-0601
Fig. 6 Low Level Output Current vs. Temperature
60
VOL - LOW LEVEL OUTPUT VOLTAGE (V)
CC
IOL - LOW LEVEL OUTPUT CURRENT (mA)
V 55 50 45 40
CC
= 5V
0.7 0.6 0.5
VE = 2V IF = 5mA
VE = 2V VOL = 0.6V
IF = 10-15mA
IO = 12.8mA 0.4 0.3 0.2 0.1 0.0 -40 -20 0 20 40 60 80 100 IO = 6.4mA IO = 9.6mA IO = 16mA
IF = 5mA 35 30 25 20 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
Fig. 7 Propagation Delay vs. Temperature
100 V 90
CC
Fig. 8 Propagation Delay vs. Pulse Input Current
90 V
CC
= 5V
= 5V
IF = 7.5mA
TP - PROPAGATION DELAY (ns)
80 70 60 50 40 30 20 -40 -20 0 20 40 60 80 100 tPLH RL = 350 tPHL RL = 350 & 1k tPLH RL = 1k
TP - PROPAGATION DELAY (ns)
80
TA = 25C
70
tPLH RL = 1k
60 tPLH RL = 350
50
40
tPHL RL = 350 & 1k
30
20 5 7 9 11 13 15
TA - TEMPERATURE (C)
IF - PULSE INPUT CURRENT (mA)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
Fig. 9 Typical Enable Propagation Delay vs. Temparature
90 V = 5V
HCPL-0601
Fig. 10 Typical Rise and Fall Time vs. Temperature
240 V 200
CC
tE - ENABLE PROPAGATION DELAY (ns)
CC
= 5V
80 70 60 50 40 30 20 10 0 -40
VEH = 3V VEL = 0V IF = 7.5mA
IF = 7.5mA
tELH RL = 1k
tf - FALL TIME (ns)
tr RL = 1k 160
tELH RL = 350
120
80 tr RL = 350 40 tf RL = 350 & 1k -40 -20 0 20 40 60 80 100
tEHL RL = 350 & 1k
0
-20 0 20 40 60 80 100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
Fig. 11 Typical Pulse Width Distortion vs. Temperature
40 V = 5V
PWD - PULSE WIDTH DISTORTION (ns)
CC
35 30 25
IF = 7.5mA
RL = 1k 20 15 10 RL = 350 5 0 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE (C)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
Pulse Generator tr = 5ns Z O = 50
+5V
I F = 7.5 mA
1 2
Input Monitor (I F) 47
VCC
8 7 6
CL .1 f bypass RL Output (VO )
Input (I F) t PHL Output (VO ) tPLH
I F = 3.75 mA
1.5 V 90% 10% tf tr
3 4
GND
Output (VO )
5
Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf. T
Pulse Generator tr = 5ns Z O = 50 Input Monitor (V E) +5V
3.0 V VCC
1
7.5 mA
8 7 6
CL RL Output (VO )
Input (VE ) t EHL t ELH
1.5 V
2 3 4
.1f bypass
Output (VO ) 1.5 V
GND
5
Fig. 13 Test Circuit tEHL and tELH. T
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
VCC
1
IF A B VFF
8 7 6 5
.1f bypass
+5V
2 3 4
350 Output (VO)
GND
VCM Pulse Gen
Peak VCM 0V
5V Switching Pos. (A), IF = 0 VO VO (Min)
CM H
VO (Max) Switching Pos. (B), IF = 7.5 mA CM L
VO 0.5 V
Fig. 14 Test Circuit Common Mode Transient Immunity T
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
8-Pin Small Outline
0.024 (0.61)
0.060 (1.52) 0.275 (6.99) 0.155 (3.94)
0.050 (1.27)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
ORDERING INFORMATION
Order Entry Identifier .R1 .R2
HCPL-0601
Option R1 R2
Description Tape and Reel (500 per Reel) Tape and Reel (2500 per Reel)
MARKING INFORMATION
1
0600 V X YY S
2
6
3
4
5
Definitions
1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) One digit year code, e.g., `3' Two digit work week ranging from `01' to `53' Assembly package code
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600
Carrier Tape Specifications
8.0 0.1 3.5 0.2 0.3 MAX 4.0 0.1 2 0.05 O1.5 MIN 1.75 0.10
HCPL-0601
5.5 0.05 8.3 0.1 5.2 0.2 12.0 0.3
0.1 MAX User Direction of Feed
6.4 0.2
O1.5 + 0.1/-0
Reflow Profile
300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 245C peak
230C, 10-30 s
Time above 183C, 120-180 sec Ramp up = 2-10C/sec * Peak reflow temperature: 245C (package surface temperature) * Time of temperature higher than 183C for 120-180 seconds * One time soldering reflow is recommended 3.5 4 4.5
3
Time (Minute)
(c) 2004 Fairchild Semiconductor Corporation
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2004 Fairchild Semiconductor Corporation
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1/7/04

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